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1 of 14 features ? real - time clock keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years ? 8k x 8 nv sram directly replaces volatile static ram or eeprom ? embedded lithium energy cell maintains cal endar operation and retains ram data ? watch function is transparent to ram operation ? automatic leap year compensation valid up to 2100 ? lithium energy source is electrically disconnected to retain fr eshness until power is applied for the first time ? standard 28 - pin jedec pinout ? full 10% operating range ? accuracy is better than 1 minute/month at +25c ? over 10 years of data retention in the absence of power ? avai lable in 120ns access time ? underwriters laborator ies (ul) recognized ( www.maxim - ic.com/qa/info/ul ) pin configuration ordering information pa rt temp range pin - package DS1243Y - 120+ 0c to +70c 28 edip (0.720a) + denotes a lead(pb) - free/rohs - compliant package . encapsulated package (720 - mil extended) a7 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 v cc we n.c. a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq3 dq4 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 15 16 a12 a6 a4 rst DS1243Y top view DS1243Y 64k nv sram with phantom clock 19 - 6 07 6 ; rev 11 /11
DS1243Y 2 of 14 pin description pin name function 1 rst active - low reset input. this pin has an internal pullup resistor connected to v cc . 2 a12 address inputs 3 a7 4 a6 5 a5 6 a4 7 a3 8 a2 9 a1 10 a0 23 a11 21 a10 24 a9 25 a8 11 dq0 data in/data out 12 dq1 13 dq2 15 dq3 16 dq4 17 dq5 18 dq6 19 dq7 20 ce active - low chip - enable input 22 oe active - low output - enable input 26 n.c. no connection 27 we active - low write - enable input 28 v cc power - supply input 14 gnd ground description the DS1243Y 64k nv sram with phantom clock is a fully static nonvolatile ram (organized as 8192 words by 8 bits) with a built - in real time clock. the DS1243Y has a self - contained lithium energy source and control circuitry, which constantly mon itors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent corrupted data in both the memory and real time clock. the phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. the phantom clock operates in either 24- hour or 12 - hour format with an am/pm indicator.
DS1243Y 3 of 14 ram read mode the DS1243Y executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enab le) is active (low). the unique address specified by the 13 address inputs (a0 C a12) defines which of the 8192 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address in put signal is stable, providing that ce and oe (output enable) access times and states are also satisfied. if oe and ce access times are not satisfied, then data access mus t be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. ram write mode the ds124 3y is in the write mode whenever the we and ce signals are in the active (low) state after address inputs are stable. the latter occurring falling edge of ce or we will det ermine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to th e high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus has been enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the DS1243Y provides full functional capability for v cc greater than v tp and write protects by 4.25v. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static ram constantly monitors v cc . should the supply voltage decay, the ram automatically write protects itself. all inputs to the ram become dont care and all outputs are high impedance. as v cc falls below approximately 3.0v, the power switching circuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0v, the power switching circuit con nects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.5v. see conditions of acceptability at www.maxim - ic.com/techsupport /qa/ntrl.htm freshness seal each DS1243Y is shipped from maxim with its lithium energy source disconnected, insuring full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation.
DS1243Y 4 of 14 phantom clock operation communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on dq0 . all accesses which occur prior to recognition of the 64 C bit pattern are directed to memory. after recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. data trans fer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable ( ce ), output enable ( oe ), and write enable ( we ). initially, a read cycle to any me mory location using the ce and oe control of the phantom clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64 C bit comparison register. next, 64 consecutive write cycles are e xecuted using the ce and we control of the smartwatch. these 64 write cycles are used only to gain access to the phantom clock. therefore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one address location in ram as a phantom clock scratch pad. when the first write c ycle is executed, it is compared to bit 0 of the 64 C bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as descri bed above until all the bits in the comparison register have been matched (this bit pattern is shown in figure 1). with a correct match for 64 bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. the next 6 4 cycles will cause the phantom clock to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock. phantom clock register information the phantom clock information is contained in 8 registers of 8 bits, each of which is sequent ially accessed 1 bit at a time after the 64 C bit pattern recognition sequence has been completed. when updating the phantom clock registers, each register must be handled in groups of 8 bits. writing and reading individual bits within a register could produ ce erroneous results. these read/write registers are defined in figure 2. data contained in the phantom clock register is in binary coded decimal format (bcd). reading and writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of register 0 and ending with bit 7 of register 7.
DS1243Y 5 of 14 phantom clock register definition figure 1 note: the pattern recognition in hex is c5, 3a, a3, 5c , c5, 3a, a3, 5c. the odds of this pattern being accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb.
DS1243Y 6 of 14 phantom clock register definition figure 2 am - pm/12/24 mode bit 7 of the hours register is define d as the 12 - or 24 - hour mode select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the 20- hour bit (20 C 23 hours). oscillator and reset bits bits 4 a nd 5 of the day register are used to control the reset and oscillator functions. bit 4 controls the reset (pin 1). when the reset bit is set to logic 1, the reset input pin is ignored. when the reset bit is set to logic 0, a low input on the reset pin will cause the phantom clock to abort data transfer without changing data in the watch registers. bit 5 controls the oscillator. when set to logic 1, th e oscillator is off. when set to logic 0, the oscillator turns on and the watch becomes operational. these bits are shipped from the factory set to a logic 1, oscillator off. zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits that always r ead logic 0. when writing these locations, either a logic 1 or 0 is acceptable.
DS1243Y 7 of 14 absolute maximum ratings voltage range on any pin relative to ground.. - 0.3v to + 6 .0v operating temperature range...0 c to +70 c (noncondensing) storage temperature range... - 40 c to + 85 c (noncondensing) lead temperature (soldering, 10 s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260 c note: edip is wave or hand - soldered only. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is no t implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended operating conditions (t a = 0 c to +70c) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v input logic 1 v ih 2.2 v cc +0.3 v input logic 0 v il - 0.3 +0.8 v dc electrical characteristics (v cc = 5v 10%, t a = 0 c to +70 c.) parameter symbol min typ max units notes input leakage current i il - 1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io - 1.0 +1.0 a output current @ 2.4v i oh - 1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2. 2 i ccs1 5.0 10 ma standby current ce = v cc C 0.5v i ccs2 3.0 5.0 ma operating current t cyc = 200ns i cc01 85 ma write protection voltage v tp 4.25 4.5 v dc test conditions outputs are open; all voltages are referenced to gro und. capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf
DS1243Y 8 of 14 memory ac electrical characteristics (v cc = 5.0v 10%, t a = 0 c to +70 c.) parameter symbol DS1243Y - 120 units notes min max read cycle time t rc 120 ns access time t acc 120 ns oe to output valid t oe 60 ns ce to output valid t co 120 ns oe or ce to output active t coe 5 ns 5 output high - z f rom deselection t od 40 ns 5 output hold from address change t oh 5 ns write cycle time t wc 120 ns write pulse width t wp 90 ns 3 address setup time t aw 0 ns write recovery time t wr 20 ns output high - z from we t odw 40 ns 5 output active from we t oew 5 ns 5 data setup time t ds 50 ns 4 data hold time from we t dh 20 ns 4 ac test conditions output load: 50pf + 1ttl gate input pulse levels: 0 to 3v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns
DS1243Y 9 of 14 phantom clock ac electrical characteristics (v cc = 4.5v to 5.5v, t a = 0c to +70c.) parameter symbol min typ max units notes read cycle time t rc 120 ns ce acces s time t co 100 ns oe access time t oe 100 ns ce to output low - z t coe 10 ns oe to output low - z t oee 10 ns ce to output high - z t od 40 ns 5 oe to output high - z t odo 40 ns 5 read recovery t rr 20 ns write cycle time t wc 120 ns write pulse width t wp 100 ns write recovery t wr 20 ns 10 data setup time t ds 40 ns 11 data hold time t dh 10 ns 11 ce pulse width t cw 100 ns reset pulse width t rst 200 ns ce high to power - fail t pf 0 ns power - down/power - up timing parameter symbol min typ max units notes ce at v ih before power - down t pd 0 s v cc slew from 4.5v to 0v ( ce at v ih ) t f 300 s v cc slew from 0v to 4.5v ( ce at v ih ) t r 0 s ce at v ih after power - up t rec 2 ms (t a = +25c) parameter symbol min typ max units notes expected data - retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery - backup mode.
DS1243Y 10 of 14 memory read cycle (note 1) memory write cycle 1 (notes 2, 6, and 7)
DS1243Y 11 of 14 memory write cycle 2 (notes 2 and 8) reset for phantom clock read cycle to phantom clock
DS1243Y 12 of 14 write cycle to phantom clock power - down/power - up condition
DS1243Y 13 of 14 notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 50pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. t he expected t dr is defined as cumulative time in the absence of v cc with the clock oscillator running. 10. t wr is a function of the latter occurring edge of we or ce . 11. t dh and t ds are a function of the first occurring ed ge of we or ce . 12. rst (pin1) has an internal pull up resistor. 13. real - time clock modules can be successfully processed through conventional wave - soldering techniques as long as temperature exposure to the lithium energ y source contained within does not exceed +85c. post - solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. package information for the latest package outline information and land patterns (footprint s), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the packag e regardless of rohs status. package type package code outline no. land pattern no. 28 edip mdt28+ 1 21- 0245
DS1243Y 14 of 14 m axim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circ uit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. ma xim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 11/11 u pdate d the features , ordering information , am - pm/12/24 mode , and absolute maximum ratings sections 1, 6 , 7

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